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MC10EP116, MC100EP116 3.3 V / 5 V Hex Differential Line Receiver/Driver
Description
The MC10EP116/100EP116 is a 6-bit differential line receiver based on the EP16 device. The 3.0 GHz bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device. Note that the input clamp will take affect only if both inputs fall 2.5 V below VCC. The 100 Series contains temperature compensation.
Features
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MCxxx EP116 AWLYYWWG LQFP-32 FA SUFFIX CASE 873A
1
1
32
QFN32 MN SUFFIX CASE 488AM xxx A WL, L YY, Y WW, W G or G
MCxxx EP116 AWLYYWWG G
* 260 ps Typical Propagation Delay * Maximum Frequency > 3 GHz Typical * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V * NECL Mode Operating Range: VCC = 0 V * * * * *
with VEE = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State Safety Clamp on Inputs Q Output Will Default LOW with Inputs Open or at VEE VBB Output Pb-Free Packages are Available
= 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
December, 2006 - Rev. 11
1
Publication Order Number: MC10EP116/D
MC10EP116, MC100EP116
D4 D5 D5 Q5 Q5 Q4 Q4 VCC D0 24 D4 D3 D3 VEE D2 D2 D1 D1 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 VCC Q3 Q3 VCC VCC Q2 Q2 VCC D3 D3 D4 D4 D5 D5 D4
24
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5
D0 D1 D1 D2 D2
MC10EP116 MC100EP116
13 12 11 10 9
D0
D0 VBB Q0 Q0 Q1 Q1 VEE
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
D5 D5
23 22
Q5 Q5
21 20
Q4 Q4 VCC
19 18 17 16 15 14 13 12 11 10 9
VBB VCC Q3 Q3 VCC VCC Q2 Q2 VCC VEE
D4 D3 D3 VEE D2 D2 D1 D1
25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
Figure 3. Logic Diagram
Exposed Pad (EP)
Table 1. PIN DESCRIPTION
PIN D[0:5]*, D[0:5]* Q[0:5], Q[0:5] VBB VCC VEE FUNCTION ECL Differential Data Inputs ECL Differential Data Outputs Reference Voltage Output Positive Supply Negative Supply
D0 D0 VBB Q0
Q0 Q1 Q1 VEE
Figure 2. 32-Lead QFN Pinout (Top View)
* Pins will default LOW when left open.
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MC10EP116, MC100EP116
Table 2. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 2 - Value 75 kW N/A > 2 kV > 100 V > 2 kV Pb-Free Pkg Level 2 Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP-32 QFN-32 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
UL-94 V-0 @ 0.125 in 729 Devices
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MC10EP116, MC100EP116
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm 2S2P 32 LQFP 32 LQFP 32 LQFP 32 QFN 32 QFN 32 QFN Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 80 55 12 to 17 31 27 12 265 265 Units V V V mA mA C C C/W C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 4. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) Input HIGH Current Input LOW Current 0.5 Min 60 2165 1365 2090 1365 1790 2.0 1890 Typ 75 2290 1490 Max 90 2415 1615 2415 1690 1990 3.3 Min 60 2230 1430 2155 1460 1855 2.0 1955 25C Typ 80 2355 1555 Max 95 2480 1680 2480 1755 2055 3.3 Min 60 2290 1490 2215 1490 1915 2.0 2015 85C Typ 85 2415 1615 Max 95 2540 1740 2540 1815 2115 3.3 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 3. All loading with 50 W to VCC - 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP116, MC100EP116
Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) Input HIGH Current Input LOW Current 0.5 Min 60 3865 3065 3790 3065 3490 2.0 3590 Typ 75 3990 3190 Max 90 4115 3315 4115 3390 3690 5.0 Min 60 3930 3130 3855 3130 3555 2.0 3655 25C Typ 80 4055 3255 Max 95 4180 3380 4180 3455 3755 5.0 Min 60 3990 3190 3915 3190 3615 2.0 3715 85C Typ 85 4115 3315 Max 95 4240 3440 4240 3515 3815 5.0 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 6. All loading with 50 W to VCC - 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 6. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 8)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 9) Output LOW Voltage (Note 9) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) Input HIGH Current Input LOW Current 0.5 Min 60 -1135 -1935 -1210 -1935 -1510 -1410 Typ 75 -1010 -1810 Max 90 -885 -1685 -885 -1610 -1310 0.0 Min 60 -1070 -1870 -1145 -1870 -1445 -1345 25C Typ 80 -945 -1745 Max 95 -820 -1620 -820 -1545 -1245 0.0 Min 60 -1010 -1810 -1085 -1810 -1385 -1285 85C Typ 85 -885 -1685 Max 95 -760 -1560 -760 -1485 -1185 0.0 Unit mA mV mV mV mV mV V
VEE+2.0
VEE+2.0
VEE+2.0
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. 9. All loading with 50 W to VCC - 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP116, MC100EP116
Table 7. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) Input HIGH Current Input LOW Current 0.5 Min 60 2155 1355 2075 1355 1775 2.0 1875 Typ 75 2280 1480 Max 90 2405 1605 2420 1675 1975 3.3 Min 60 2155 1355 2075 1490 1775 2.0 1875 25C Typ 80 2280 1480 Max 95 2405 1605 2420 1675 1975 3.3 Min 60 2155 1355 2075 1490 1775 2.0 1875 85C Typ 85 2280 1480 Max 95 2405 1605 2420 1675 1975 3.3 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 12. All loading with 50 W to VCC - 2.0 V. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 14)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 15) Output LOW Voltage (Note 15) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 16) Input HIGH Current Input LOW Current 0.5 Min 60 3855 3055 3775 3790 3475 2.0 3575 Typ 75 3980 3180 Max 90 4105 3305 4120 3375 3675 5.0 Min 60 3855 3055 3775 3190 3475 2.0 3575 25C Typ 80 3980 3180 Max 95 4105 3305 4120 3375 3675 5.0 Min 60 3855 3055 3775 3190 3475 2.0 3575 85C Typ 85 3980 3180 Max 95 4105 3305 4120 3375 3675 5.0 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 15. All loading with 50 W to VCC - 2.0 V. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP116, MC100EP116
Table 9. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 17)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 18) Output LOW Voltage (Note 18) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) Input HIGH Current Input LOW Current 0.5 Min 60 -1145 -1945 -1225 -1945 -1525 -1425 Typ 75 -1020 -1820 Max 90 -895 -1695 -880 -1625 -1325 0.0 Min 60 -1145 -1945 -1225 -1945 -1525 -1425 25C Typ 80 -1020 -1820 Max 95 -895 -1695 -880 -1625 -1325 0.0 Min 60 -1145 -1945 -1225 -1945 -1525 -1425 85C Typ 85 -1020 -1820 Max 95 -895 -1695 -880 -1625 -1325 0.0 Unit mA mV mV mV mV mV V
VEE+2.0
VEE+2.0
VEE+2.0
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. Input and output parameters vary 1:1 with VCC. 18. All loading with 50 W to VCC - 2.0 V. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)
-40C Symbol fmax tPLH, tPHL tSKEW tSKEW tJITTER VPP tr tf Characteristic Maximum Frequency (See Figure 4 Fmax/JITTER) Propagation Delay to Output Differential Duty Cycle Skew (Note 21) Within Device Skew Device to Device Skew (Note 21) Cycle-to-Cycle Jitter (See Figure 4 Fmax/JITTER) Input Voltage Swing (Differential Configuration) Output Rise/Fall Times (20% - 80%) Q, Q 150 90 0.2 800 150 160 Min Typ >3 250 5.0 340 20 100 180 <1 1200 220 150 90 0.2 800 160 160 Max Min 25C Typ >3 260 5.0 340 20 100 180 <1 1200 240 150 90 0.2 800 160 190 Max Min 85C Typ >3 300 5.0 380 20 100 190 <1 1200 250 Max Unit GHz ps ps ps ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 21. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs.
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MC10EP116, MC100EP116
900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0 9 JITTEROUT ps (RMS) 8 7 6 5 4 3 2 (JITTER) 4000 1 5000
0
1000
2000
3000
FREQUENCY (MHz)
Figure 4. Fmax/Jitter
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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EE EE
EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE
MC10EP116, MC100EP116
ORDERING INFORMATION
Device MC10EP116FA MC10EP116FAG MC10EP116FAR2 MC10EP116FAR2G MC10EP116MNG MC10EP116MNR4G MC100EP116FA MC100EP116FAG MC100EP116FAR2 MC100EP116FAR2G MC100EP116MNG MC100EP116MNR4G Package LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) QFN-32 (Pb-Free) QFN-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) QFN-32 (Pb-Free) QFN-32 (Pb-Free) Shipping 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel 74 Units / Rail 1000 / Tape & Reel 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel 74 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10EP116, MC100EP116
PACKAGE DIMENSIONS
32 LEAD LQFP CASE 873A-02 ISSUE C
A
25 4X
32
A1
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V V1
AE P AE
17
DETAIL Y
BASE METAL
9
S
8X
M_
R
J
G -AB-
SEATING PLANE
DETAIL AD CE
SECTION AE-AE
-AC- 0.10 (0.004) AC 0.250 (0.010) H W X DETAIL AD K Q_
GAUGE PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION.
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
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10
0.20 (0.008)
9
-Z-
S1
0.20 (0.008) AC T-U Z
F
D
M
4X
EE EE EE EE
N
AC T-U Z
DETAIL Y
-T-, -U-, -Z-
MC10EP116, MC100EP116
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE O
D A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X
8
1
b 0.10 C A B
32 X
0.05 C BOTTOM VIEW
32 X
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE
TOP VIEW SIDE VIEW
9
PIN ONE LOCATION
E
(A3) A A1 C
EXPOSED PAD 16 SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
D2
K
17 32 X
SOLDERING FOOTPRINT*
5.30 3.20 0.63
32 X
E2
24 32 25
e
3.20
5.30
0.28
0.50 PITCH
28 X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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11
MC10EP116/D

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